Full Description

Scope

This standard describes a computer backplane bus optimized for 32-bit transfers, multiprocessor operations, and simplicity. In brief, this is a synchronous (10 MHz), multiplexed, multimaster bus that provides a strictly fair arbitration mechanism. The only bus transfers are read and write (and block transfer versions of each of these) to a single 32-bit address space. Geographic slot addressing and nondaisy-chain arbitration scheme make system configuration simpler by eliminating switches and jumpers. This minimalist approach results in a conceptually straightforward bus with a small pin count (51 active signal lines). Figure shows the major elements of a typical NuBus system.

Purpose

This standard is intended to describe and specify the logical, electrical, and physical interface standard for circuit boards that allow them to connect to and communicate over a backplane. It also specifies the backplane environment that must be provided to these boards. This standard is oriented to designers of bus interface logic, designers of backplane environments, and those evaluating buses. In keeping with the minimalist philosophy of the bus, the standard has taken a similar approach. Section 2. provides an introduction to the bus, Section 3. is the minimalist core of the specification, and Appendix A describes implications and capabilities that follow from the rules presented in Section 3. Not specified by this standard are:- Physical Environment--This includes topics such as how a backplane attaches to a rack, provisions for system cooling, resistance to vibration, etc. - system Architecture--This is a low-level specification. Any system architectures (such as message passing protocols) are not within the scope of this standard.

Abstract

New IEEE Standard - Inactive-Withdrawn.Withdrawn Standard. Withdrawn Date: Mar 06, 2000. No longer endorsed by the IEEE. A simple, high-performance (37.5 Mbyte/s) backplane bus that provides the functions required by multiprocessor systems is defined. NuBus is a synchronous (10 MHz), multiplexed, multimaster bus that provides a fair arbitration mechanism. The logical, electrical, and physical interface standard for circuit boards that allows them to connect to and communicate over a backplane, as well as the backplane environment that must be provided to these boards, is described and specified. The protocol specification covers signal determinacy, bus cycles, transactions, block transfers, attention cycles, arbitration, address space, and utility functions. The physical specification covers timing, dc and ac specifications for signals, backplane (signal) characteristics, voltage and mechanical specifications for triple-height modules. Compliance requirements are stated. Concepts required for a general understanding of the NuBus specification, covering bus lines and bus operation, are included. This document also contains ANSI/IEEE Std 1101-1987, IEEE Standard for Mechanical Core Specifications for Microcomputers.

Product Details

Published: 08/08/1988 ISBN(s): 1559376821, 9780738123479 Number of Pages: 61File Size: 1 file , 630 KB Product Code(s): STDWD11601