Full Description

Scope

This document provides recommendations for the layout and test methods required to properly characterize the latchup behavior in CMOS and BiCMOS integrated-circuit processes or other processes that have similar lateral PNPN topographical layout characteristics.

Purpose

This recommended practice is intended to provide recommendations to enable the characterization of an integrated-circuit process architecture. This document describes how to characterize worst-case CMOS integrated-circuit layout topography for PNPN latchup. This document is intended to be used to test the behavior of a CMOS process, and not a CMOS product. Establishing a recommended practice allows the scientific comparison of different approaches to processes or process architectures by establishing a workable methodology of topographical layout and electrical measurement procedures. By doing so, technical papers can be written so that comparisons of different engineering approaches can be better made. Establishing a recommended practice allows the scientific comparison of similar CMOS processes so that a purchaser of custom integrated circuits can use a common test methodology to evaluate and compare the processes of one or more vendors or foundries of custom integrated circuits. This allows the evaluation of the process capabilities on a worst-case recommended structure and test method independent of actual integrated-circuit product topological latchup layout practices (which should be topographically best-case layouts, and not worst-case layouts). It is not the purpose of this recommended practice to be applied to semiconductor products. For product testing, EIA/JEDEC JC-40.2-87-16 [1] should be used.

Abstract

New IEEE Standard - Inactive-Withdrawn.Withdrawn Standard. Withdrawn Date: Mar 06, 2000. No longer endorsed by the IEEE. Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit processes or other processes that have similar lateral PNPN topographical layout characteristics. The aim is to allow the characterization of an integrated circuit process architecture so that different approaches can be scientifically compared. This allows the evaluation of the process capabilities on a worst-case recommended structure and test method independent of an actual integrated circuit product topographical latchup layout practices. Test structures and test philosophy are covered.

Product Details

Published: 12/13/1991 ISBN(s): 1559371528, 9780738123882 Number of Pages: 36File Size: 1 file , 970 KB Product Code(s): STDWD14605